Clocking is implemented in highly integrated system-on-chips (SoCs) using a clock tree that is automatically synthesized using engineering design aid (AID) tools. The clock is propagated using a single path along which many buffers are used to couple the clock signal from the point of generation to various destinations (e.g., “leaf” cells). However, the buffers used to build this tree have varying degrees of delay, which causes phase differences in the clock signal at different points of the destinations. The varying degrees of delay are compounded because different branches of the clock trees have different degrees of delay. Further, the degrees of delay can vary in a nonlinear fashion as a function of voltage.